3DXP's Memory Role Unclear
posted on June 05, 2017 11:42
In integrated circuits, interconnect resistance is a combination of wire and via resistance. Wire resistance of a conductor depends on several factors, one of which is the electron scattering at various surfaces and grain boundaries. Via resistance, on the other hand, is a function of the thickness or resistivity of the layers at the bottom of the via through which current must travel.
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TSMC plans trial production of advanced 5nm process in 2019
posted on June 05, 2017 11:41
TAIPEI, Taiwan -- Taiwan Semiconductor Manufacturing Co. (TSMC, 台積電), the world's largest contract chip maker, is planning to start production of chips made using the sophisticated 5 nanometer process on a trial basis in 2019.
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Samsung Unveils Scaling, Packaging Roadmaps
posted on June 05, 2017 11:40
Samsung Foundry unveiled an aggressive roadmap that scales down to 4nm, and which includes a fan-out wafer-level packaging technology that bridges chips in the redistribution layer, 18nm FD-SOI, and a new organizational structure that allows the unit much greater autonomy as a commercial enterprise.
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Views of the Silicon Roadmap
posted on May 25, 2017 15:05
ANTWERP, Belgium — The semiconductor road map that An Steegen is showing this year has a new node in the upper right hand corner — 14 Å. The placeholder for a 14-angstrom process — a 0.7x shrink from a 2-nm node in 2025 — is a sign of the unflagging optimism of the veteran process technology expert at the Imec research institute
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The Race To 10/7nm
posted on May 25, 2017 15:04
Amid the ongoing ramp of 16/14nm processes in the market, the industry is now gearing up for the next nodes. In fact, GlobalFoundries, Intel, Samsung and TSMC are racing each other to ship 10nm and/or 7nm technologies.
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Global Foundaries says EUV Production in 2019
posted on May 25, 2017 15:03
Globalfoundries will introduce 7nm FinFET production using optical immersion lithography with tape outs expected in the first quarter of 2018, according to Gary Patton, chief technology officer of the foundry.
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Making Interconnects Faster
posted on May 25, 2017 15:02
In integrated circuits, interconnect resistance is a combination of wire and via resistance. Wire resistance of a conductor depends on several factors, one of which is the electron scattering at various surfaces and grain boundaries. Via resistance, on the other hand, is a function of the thickness or resistivity of the layers at the bottom of the via through which current must travel.
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Extending EUV Beyond 3nm
posted on May 25, 2017 15:01
Now that EUV is finally shipping, companies are working on extending it much further using anamorphic lenses and high numerical aperture technology.
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Samsung completes qualification of its 2nd gen 10nm process technology
posted on April 25, 2017 07:05
Samsung Electronics Co., Ltd. announced today that its second generation 10-nanometer (nm) FinFET process technology, 10LPP (Low Power Plus), has been qualified and is ready for production.
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3D NAND flash output set to expand in 2H17
posted on April 25, 2017 07:04
The global output of 3D NAND flash memory chips is set to expand substantially in the second half of 2017, and will exceed that of 2D NAND chips in the fourth quarter of the year, according to industry sources.
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