ADVANCED CMOS TECHNOLOGY 2016 (THE 20/14/10 NM NODES)
The course has been newly updated to include all of the latest developments in CMOS technology and will be technically current for 2016.
The relentless drive in the semiconductor industry for smaller, faster and cheaper integrated circuits has driven the industry to the 14 nm node and ushered in a new era of high-performance 3-dimensional transistor structures. The speed, computational power, and enhanced functionality of ICs based on this advanced technology promise to transform both our work and leisure environments. However, the implementation of this technology has opened a Pandora’s box of manufacturing issues as well as set the stage for a range of manufacturing challenges that require revolutionary new process methodologies as well as innovative, new equipment for the 20/14nm and the upcoming 10/7nm nodes. This seminar addresses all of these manufacturing issues with technical depth and conceptual clarity, and presents leading-edge process solutions to the new and novel set of problems presented by 20nm and 14 nm FinFET technology and previews the upcoming manufacturing issues of the 10/7 nm nodes.
The central theme of this seminar is an in-depth presentation of the key 20/14/10 nm node technical issues: CD control, defectivity, high-k/metal gate, EUV lithography, mobility enhancement, Copper/low-k integration and FinFet, planar and SOI devices. Processing details of 3D Flash memory will be presented as well as a detailed 7m nanowire processing sequence.
A detailed technology roadmap for the future of Logic, Flash and DRAM process integration, as well as 3D packaging and 3D Monolithic fabrication will also be presented.
Each section of the course will present the relevant technical issues in a clear and comprehensible fashion as well as discuss the proposed range of solutions and equipment requirements necessary to resolve each issue. In addition, the lecture notes are profusely illustrated with extensive 3D illustrations rendered in full-color.
Download this seminar brochure as a .pdf file
|To Be Announced
SEMI Headquarters 3081 Zanker Road, San Jose, California, 95134
- Three days of instruction by industry experts with comprehensive, in-depth knowledge of the subject material
- A high quality set of full-color lecture notes (a $495 value), including SEM & TEM micrographs of real- world IC structures that illustrate key points
- Continental breakfast, hot buffet lunch, and coffee, beverages, & snacks served at both morning and afternoon breaks
Who is the seminar intended for:
- Equipment Suppliers & Metrology Engineers
- Fabless Design Engineers and Managers
- Foundry Interface Engineers and Managers
- Device and Process Engineers
- Design Engineers
- Product Engineers
- Process Development & Process Integration Engineers
- Process Equipment Marketing Managers
- Materials Supplier Marketing Managers & Applications Engineers
1. Process integration. The 14nm technology nodes represents a landmark in semiconductor manufacturing and it employs transistors that are substantially faster than anything ever previously fabricated. However, such performance comes at a significant increase in processing complexity and requires the solution of some very fundamental scaling and fabrication issues, as well as the introduction of radical, new approaches to semiconductor manufacturing. This section of the course highlights the key changes introduced at the 14nm and describes the technical issues that had to be resolved in order to make this node a reality.
- The enduring myth of a technology node
- Market forces: the shift to mobile
- The Idsat equation
- The motivations for High-k/Metal gates, strained Silicon,
- Device scaling metrics
- Ion/Ioff curves, scaling methodology
2. Detailed 20nm Planar Fabrication Sequence. The key to rapidly understanding any new technology is to view it in its entirety. This approach provides a context and a perspective that the study of isolated technical components cannot. Once a sense of technical perspective is established, the student can "drill-down" into each technical area of interest and expand their understanding of the subject matter. This portion of the seminar presents a detailed 20nm front–end Logic process flow.
The purpose of this section of the course is to establish a baseline understanding of the 2nm technology node and to provide a fundamental framework for the subsequent in-depth presentations on each technical issue. The underlying purpose of each processing operation is discussed and the processing options and equipment considerations for each major module highlighted. Three-dimensional graphics are used throughout this presentation to better illustrate the micro-architectures and to clarify the concepts being presented.
The topics covered include:
- A detailed step-by-step 20nm fabrication process flow
- Front End Of Line (FEOL) processing options and technical considerations
- High-k/Metal gate, strain, and salicide integration techniques
- Gate-first and Gate-Last integration methodologies
3. Detailed 14nm FinFET Fabrication Sequences. The FinFet represents a radical departure in transistor architecture. It also presents dramatic performance increases as well as novel fabrication issues. The 14nm FinFETs is the 2nd generation of non-planar transistor and it involves some radical changes in manufacturing methodology. The FinFET’s unusual structure makes its architecture difficult for even experienced processing engineers to understand. This section of the course drills down into the details of 14nm FinFet structure and fabrication, highlighting the novel manufacturing issues this new type of transistor presents. A detailed step-by-step 14nm fabrication sequence is presented that employs colorful 3D graphics to clearly and effectively communicate the novel FinFET architecture at each step of the fabrication process. Attention to key manufacturing pitfalls and specialty requirements are pointed out at each phase of the manufacturing process.
- A detailed step-by-step 14nm FinFET fabrication process flow
- Bulk and SOI FinFET integration
- FinFET High-k/Metal Gate integration
- Gate-first and Gate-Last integration methodologies
- Contact options, including Copper contacts
- Manufacturing issues, roadblocks and solutions
4. The transition from 22nm to 14nm FinFET Technology. For most manufactures the technology of choice at the 14nm node is bulk silicon and not SOI. These devices use scaled gate lengths, aggressive Self-Aligned Double Patterning, Solid State Doping and a scaled fin structure. This section of the course will contrast and compare 14nm node FinFET processing to 22nm FinFET processing and highlight the differences in their structure and manufacturing methodologies. Numerous 3D color illustrations are used to clearly convey the structure and processing details of these two technology nodes.
- Self Aligned Double Patterning and Self-Aligned Quadruple Patterning
- Carbon doped silicon source/drain fabrication methodology
- Solid Sate Fin Doping
- 14nm versus 22nm manufacturing issues
5. The 7nm Node; Nanowires? Waiting in the wings is the 7nm node. Although this node will probably be some evolutionary adaptation of a FinFET, the possibility exists that the 7nm will see the advent of a new and radically different 3D device known as a Nanowire. These highly non-classical transistors consist of an array of ultra-thin silicon wires arranged in either a horizontal or vertical orientation and which feature gate-all-around control of short channel effects and a high level of scalability. A detailed process flow of a vertical Nanowire process will be presented that is beautifully illustrated with colorful 3D graphics.
- Key fabrication details and manufacturing problems
- Vertical versus horizontal Nanowires: advantages and disadvantages
- Nanowire SCE control and scaling
6. 3D Flash Memory. Rumors of the death of Flash memory appear to have been greatly exaggerated. 3D Flash will not only dramatically increase non-volatile memory capacity, it will probably add at least three generations to the life of this memory technology. However, the structure and fabrication of this type of memory is radically different, even alien, to any traditional semiconductor fabrication methodology. This section of the course presents a step-by-step description of the unusual manufacturing methodology used to create 3D Flash memory, focusing on key problem areas and equipment opportunities.
- staircase fabrication methodology
- the role of ALD in 3D Flash fabrication
- controlling CDs in tall, vertical structures
- 3D Flash operation
7. Advanced Lithography. Lithography is the “heartbeat” of semiconductor manufacturing and is also the single most expensive operation in any fabrication process. Without further advances in lithography, continued scaling would difficult, if not impossible. However the art and science of photolithography has experienced serious delays and setbacks that have forced the development of innovative new technologies. This section of the course begins with a concise and technically correct introduction to the subject and then provides in-depth insights into the latest developments in photolithography. Special attention is paid to EUV lithography, its capability, characteristics and the technical problems delaying its introduction.
- Physical Limits of Lithography Tools
- Immersion Lithography – principles and practice
- Double, Triple and Quadruple patterning
- EUV Lithography: status, problems and solutions
- Resolution Enhancement Technologies
- Photoresist: chemically amplified resist issues
- Emerging Lithography Technologies (DSA, Imprint etc.)
8. Survey of leading edge devices. This part of the course presents a visual feast of TEMs and SEMs of real-world, leading edge devices for Logic, DRAM and Flash memory. The key architectural characteristics for a wide range of key devices will be presented and the engineering trade-offs and compromises that resulted in their specific architectures will be discussed. A representative of the world’s leading chip reverse engineering firm will present the section of the course.
9. 3D Packaging Versus 3D Monolithic Fabrication. Unlike all other forms of advanced packaging that communicate by routing signals off the chip, 3D packaging permits multiple chips to be stacked on top of each other, and to communicate with each other using Thru-Silicon Vias (TSVs), as if they were all one unified microchip. An alternate is the 3D Monolithic approach, in which one or more layers of devices are fabricated on a pre-existing device, and electrically connected together employing standard micro-dimensional interconnects. Both approaches have advantages and disadvantages and promise to create a revolution in the functionality, performance and the design of electronic systems.
This part of the course identifies the underlying technological forces that have driven the development of Monolithic fabrication and 3D packaging, how they are designed and manufactured, and what the key technical hurdles are to the widespread adoption of these revolutionary technologies.
- TSV technology: design, processing and production
- Interposers: the shortcut to 3D packaging
- The 3D Monolithic fabrication process
- Annealing 3D Monolithic structures
- The Internet of Things (IoT)
10. The Way forward: a CMOS technology forecast. Ultimately, all good things must come to an end, and the end of classical (bulk, planar) CMOS has arrived. No discussion of advanced CMOS technology is complete without a peek into the future, and this final section of the course looks ahead to the 10/7/5nm CMOS nodes and forecasts the evolution of CMOS device technology for Logic, DRAM and Flash memory.
- The two possible paths forward in CMOS device architecture (FinFETs vs UTB SOI)
- The transition to 3D devices
- Future memory technologies: OVM, RRAM, PCRAM,
- New nanoscale effects and their impact on CMOS device architecture and materials
- Is Moore’s law finally coming to an end?
- Future devices: Quantum well devices, Nanowires and Tunnel FETs