Entries for October 2018
3D NAND: Challenges Beyond 96-Layer Memory Arrays
posted on October 27, 2018 08:06
Unlike scaling practices in 2D NAND technology, the direct way to reduce bit costs and increase chip density in 3D NAND is by adding layers. In 2013, Samsung shipped the first V-NAND product using 24 layers and MLC [1].
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Advanced packaging technologies are key for semiconductor innovation
posted on October 27, 2018 08:05
“2017 was an unprecedented year for semiconductor industry,” commented Santosh Kumar, Director of Packaging, Assembly and Substrates at Yole Korea, part of Yole Développement (Yole). “The market grow by 21.6% year-to-year to reach record of almost US$412 billion.”
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Is 3D IC The Next Big Profit Driver?
posted on October 27, 2018 08:04
Changes occurring in the 3D-IC landscape may be just the beginning of a significant inflection point in the IC industry.
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Imec, ASML Team on Post-3nm Lithography
posted on October 27, 2018 08:03
LONDON — Research organization Imec and lithography equipment manufacturer ASML plan to establish a joint research lab to explore printing nanoscale devices towards the post-3nm logic node.
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China Policy Needs a Reset
posted on October 27, 2018 08:02
Handel Jones just got back from China, and he doesn’t like how the techno-
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EUV’s Uncertain Future
posted on October 27, 2018 08:01
The ground appears to be solidifying under EUV. Intel announced this week it is reducing its stake in ASML to less than 3%, the second such move in a year. Apparently ASML no longer needs outside help.
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