Advanced CMOS Technology - the 3/2nm Node
The course has been newly updated to include all of the latest developments in CMOS technology and is technically current.
The central theme of this seminar is an in-depth presentation of the key 5/3 nm node technical issues for Logic and Memory, including detailed process flows for these technologies.
This course addresses the issues associated with Advanced CMOS manufacturing with technical depth and conceptual clarity, and presents leading-edge process solutions to the new and novel set of problems presented by 5 nm FinFET technology and previews the upcoming manufacturing issues of 3nm Nanosheets.
- Three days of instruction by industry experts with comprehensive, in-depth knowledge of the subject material
- A high quality set of full-color lecture notes, including SEM & TEM micrographs of real-world IC structures that illustrate key technical points
- A Diploma stating that you have successfully completed the seminar will be mailed to you at the end of the course
1. Process integration. The 5/3 nm technology nodes represent a landmark in semiconductor manufacturing and they employs transistors that are faster and smaller than anything previously fabricated. However, such performance comes at a significant increase in processing complexity and requires the solution of some very fundamental scaling and fabrication issues, as well as the introduction of radical, new approaches to semiconductor manufacturing. This section of the course highlights the key changes introduced at the 5/3nm nodes and describes the technical issues that had to be resolved in order to make these nodes a reality.
- The enduring myth of a technology node
- Market forces: the shift to mobile
- The Idsat equation
- Ion/Ioff curves, scaling methodology
- The Standard Cell Concept
- Buried Power Rails
2. Finfet Fundamental Concepts. The FinFET is a radical new transistor with a novel architecture. Unlike the planar transistor, which has served the industry for 50+ years, the FinFET has a three-dimensional structure wherein the transistor channel in contained in a fin that rises above the surface of the substrate. This architecture provides a the advantage of greater immunity against Drain Induced Barrier Lowering (DIBL) and therefore enables continued transistor scaling. It also allows for a device with a fully depleted channel and an enhanced pacing density of transistors on the active area.
This section of the course examines the landscape of existing transistor technologies and focuses on the unique aspects of the FinFET and its structure.
- Why did planar scaling come to an end?
- What does the landscape of alternate transistor technologies look like?
- Why is the FinFet the solution to further CMOS scaling?
3. Detailed 5nm Fabrication Sequence.
The FinFET represents a radical departure in transistor architecture. It also presents dramatic performance increases as well as novel fabrication issues. The 5nm FinFET is the 5th generation of non-planar transistor and involves some radical changes in manufacturing methodology. The FinFET’s unusual structure makes its architecture difficult for even experienced processing engineers to understand. This section of the course drills down into the details of 5 nm FinFet structure and its fabrication, highlighting the novel manufacturing issues this new type of transistor presents. A detailed step-by-step 5 nm fabrication sequence is presented (Front-end and Backend) that employs colorful 3D graphics to clearly and effectively communicate the novel FinFET architecture at each step of the fabrication process. Attention to key manufacturing pitfalls and specialty material requirements are pointed out at each phase of the manufacturing process, as well as the chemistries used at each operation.
- Self-Aligned Quadruple Patterning (SAQP)
- Germanium PMOS fin fabrication
- Multiple Vt Hi-/Metal Gate integration strategies
- Cobalt Contacts & Cobalt metallization
- Contact over Active Gate methodology
- Tone Reversal Metallization methodology
- Air-gap dielectrics
4. Self-Aligned Quadruple Patterning & Selective Fin Removal. Until the
recent introduction of EUV lithography there was only a few practical ways
to fabricate extremely small fin structures: Self-Aligned Double Patterning
(SADP) and Self-Aligned Quadruple Patterning (SAQP). These fabrication
methodologies were introduced at the 22nm node, have currently reached a
state of near-perfection and are still in use for the purpose of fin
formation at the 5nm node. They offer an exceptional critical dimensional
stability and a uniformity that even EUV cannot provide.
This section of the course provides an illustrated and highly detailed
explanation of how SAQP works, and how is used to create the extremely
narrow fins used in 5nm node technology. Also presented are the
consideratins for the fabrications of SiGe PMOS fins and the selective
removal of fins located on Well boundaries.
- Extreme Ultra VIolet (EUV) Lithography - the advantages and
disadvantages with this technology
- SAQP- the alternative to EUV
- 193 nm Immersion lithography
- SiGe PMOS fin fabrication
- Cut Masks and Pitch walking
5. The Well Module. The purpose of a Well structure in traditional planar
microelectronics is to provide a channel region and to provide electrical
isolation for the PMOS and NMOS devices. In a FinFET the channel is located
above the Well in the fin structure. However, the Wells still serve the
critically important purpose of electrical isolation and are essential to
the effective functioning of the transistors.
This section of the course explains the fabrication details of the Well
structures and the key technical details of their dopant profiles as well as
the Solid State doping of that portion of the fin located in the Wells.
- Ion Implantation
- Rapid Thermal Annealing
- The Solid State Doping fabrication sequence
6. The Transitor Module. The 5nm FinFET transistor poses a
special series of fabrication problems. The Extension implants are defined using
a special plasma doping process and the Carbon Doped Spacers that accompany them
are defined in a two-step operation that uses an oversized Silicon Oxynitride
mask. These processing operations are described using a detailed series of 3D
illustrations that provide a clear and comprehensible explanation of this key
- Self-Aligned Double Patterning (SADP) of the Gate Electrode
The extension implant process and
- The Low-K spacer - purpose and fabrication methodology
7. Implementing Strained Silicon at the 5nm Node.
Strained Silicon has been the key performance enhancement technology for the
past 10 technology nodes. However, implementing strained Silicon with 5nm
FinFETs poses special problems. It involves a complicated series of operations
that remove that portion of the fins located outside of the Spacer regions
followed by the selective Epitaxial growth of SiGe and SiP crystals. This
process is illustrated step-by-step with detailed 3D graphics that demystify the
Strained Silicon process as well as presents an alternate Extension fabrication
- The role of SiCN hard masks in Strained Silicon fabrication
- The channel fin removal process
- Preserving the Extension implant during the fin removal
- Facilitating the epitaxial growth of SiGe and SiP crystals
8. Multiple Threshod Voltage Fabrication. A device with a
single threshold voltage (Vt) is of little practical use. Four or six separate
Vts (3 PMOS and 3NMOS) are required in order to have a useful microprocessor.
Fabricating transistors with multiple Vts requires a complicated and difficult
series of processing operations involving Hi-k dielectrics and a series of
differing Work Functions metals. This complex and critical fabrication process
is described in detail and illustrated in a step-by-step fashion that explains
the many processing operations required to successfully create a series of
transistors with multiple Vts.
- Why are multiple Threshold Voltages required?
- A detailed Multiple High-k/
9. Contact Over Active Gate (COAG).
Contact Over Active Gate (COAG) provides a dramatic
reduction in the active area occupied by a transistor. It also has a long and
problematic history of being extremely difficult to successfully implement in
high-volume production. COAG requires multiple etch-stops, selective etch
chemistries and precise lithographic alignment to successfully implement. This
complicated and fascinating fabrication methodology is presented and illustrated
- The advantages and the pitfalls of COAG
- Self-Aligned contacts
- Dual-etch barriers for the Gate Electrode and the Source/ Drain
10. Back-End Metallization. The smaller the technology node,
the greater the transistor count and the more levels of Copper metal required to
realize all of the interconnections between these transistors. At the 5nm node
the Copper interconnections form a Byzantine network of metal that requires some
very complex and challenging processing. The differing techniques required to
fabricate the Copper interconnections at each level of metal are presented and
illustrated in detail. The impact of the massive metal interconnections used at
the 5nm node on electrical performance is also discussed.
- SAQP metal line via and trench formation
- Dual Damascene for Copper line formation with TaN barriers and Cobalt
- Tone Reversal metallization