22nm Planar SOI Fabrication
This course covers all of the latest developments in 22nm SOI Fabrication.
This one-day course provides a step-by-step explanation of current state-of-the-art silicon fabrication focusing on the details of a 22 nm SOI Logic process flow. All aspects of the 22nm SOI fabrication process are discussed in depth and both gate-first and gate-last integration methodologies are presented. Both back-end and Front-end processes are described in detail.
The course highlights the importance of each topic it treats in the context of real world of commercial semiconductor manufacturing and is designed to provide a deeper understanding of silicon processing and the emerging new technologies that are revolutionizing this field.
The class notes are technically current, in full color and extensively illustrated with state-of-the-art 2D and 3D graphics. They feature numerous cross-sectional and top-down SEM and TEM photographs of leading edge commercial device structures.
The course is targeted at Designers, R&D, Product, Device, Test and Process engineers, managers and other personnel who desire a deeper understanding 22nm SOI Logic.
The course content is presented in a clear, highly visual and easy-to-understand manner. It is taught by a world-class instructor who has over 20 years of hands-on experience in the field of silicon fabrication and who is an award winning public speaker.
Download this seminar brochure as a .pdf file
Date: To Be Announced
Location: To Be Announced
- A full day of instruction by an industry expert with an in-depth understanding of the course material.
- A high quality set of course notes that are in full color.
- Continental breakfast, hot buffet lunch and snacks at the morning and afternoon breaks.
This course is intended for:
- Device, Test and Process engineers
- Failure analysis engineers
- Equipment engineers
- Fab interface engineers
- Patent Attorneys
- Managers and other personnel who desire a deeper understanding 22nm FinFet processing
- An introduction to SOI wafer fabrication options
22nm SOI Process Integration; the Front End:
- The performance and processing advantages of SOI
- Introduction to the basic modules
- Shallow Trench Isolation
- Raised Source/Drain fabrication details
- Double patterning and the maintenance of critical dimension control
- Planar gate electrode formation - hard masks and double patterning
- Replacement gate (gate-last) integration methodology
- High-k/metal gate integration strategies
- Strained silicon using NMOS fracture plane and SiGe replacement Source/ drains technologies
- Unique SOI processing considerations RF SOI versus Logic SOI
22nm SOI Process Integration; the Back End:
- Tungsten trench contacts
- The Dual Damascene process: metal masks, Ta/TaN barrier deposition, copper deposition and polish
- New metal resistance modalities: surface and grain boundary scattering
An Introduction to SOI FinFets:
- An overview of the FinFet manufacturing process
- Advantages and challenges of Bulk versus SOI FinFETS manufacturing
Jerry Healey has been a technical professional in the semiconductor industry for over 25 years, 8 years of which were spent as a Device Engineer at Motorola Semiconductor. He was formerly an instructor for UC Berkeley Extension (College of Engineering), and more recently was employed as a Process Integration Engineer at the Advanced Technology Development Facility, where he worked on advanced technology node development.
He is a renowned lecturer in the field of silicon processing, and his areas of expertise include process integration, technology transfer of new processes from R&D into manufacturing, 3D Packaging and FinFET fabrication. His audiences remember him for the breadth of his knowledge regarding semiconductor manufacturing, his engaging lecture style, and the insightful 3D color graphics he uses to illustrate his lectures.
An award winning public speaker, Mr. Healey has taught numerous courses to thousands of practicing engineers and scientists over the past 15 years. He has also authored numerous papers in the field of silicon processing, and is currently the president of Threshold Systems, a firm that provides consulting services and technical training seminars to the semiconductor industry.
“As a logic design engineer I've never been given any training in how the chips are physically made and I found the information in this course to be fascinating. Every hardware design engineer should take this course.” - T. Jameson
“Jerry Healey has the ability to make difficult and complex information seem easy and readily comprehensible. His color graphics are just superb.” – K. Anderson