Threshold voltage tuning for 10nm and beyond CMOS integration
posted on October 21, 2014 15:01
At very small process geometries, precise control of electrical conductivity is difficult to maintain. The industry requires a viable replacement-gate FinFET architecture to continue scaling high performance CMOS [1, 2] technology and designs. Furthermore, cost-effective and precise VT control to achieve multiple VTs is essential for future ULSI fabrication to achieve optimal power consumption and performance.
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