Entries for 'JDMLT'
Sub-10 nm nanotechnology engineering breakthrough is big deal for electronics
posted on July 29, 2013 18:10
University of Akron researchers have developed new materials that function on a nanoscale, which could lead to the creation of lighter laptops, slimmer televisions and crisper smartphone visual displays
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450mm: Out Of Sync
posted on July 29, 2013 18:09
The IC industry has been talking about it for ages, but vendors are finally coming to terms with a monumental shift in the business. The vast changes involve a pending and critical juncture, where the 450mm wafer size transition, new device architectures and other technologies will likely converge at or near the same time.
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Address FinFET test challenges
posted on July 29, 2013 18:08
FinFET technology is seen as the answer to fabrication processes below 20 nm. However, FinFET also presents a lot of uncertainty and concern related to defect manifestation, necessary test methods, and diagnosis of the defects for analysis and yield improvement.
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Precision is key to scaling below 14nm
posted on July 29, 2013 18:07
In advance of the 2013 SEMICON West TechXPOTs on lithography and nonplanar transistors beyond 20nm, SEMI asked some of the speakers and industry experts to comment on the challenges they wanted to highlight. Many of the inputs focused on the need for precision in the processes used to form transistors, as well as how EDA can contribute to mitigating variability.
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Rebirth of mask process correction for better wafer lithography
posted on July 29, 2013 18:05
Who knew that mask process correction (MPC) would again become necessary for the manufacturing of deep ultraviolet (DUV) photomasks? MPC can be called a seasoned technology; it has always been an integral part of the e-beam mask writers to cope with the e-beam proximity effects, which can extend up to 15um of the exposure point.
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DRAM Prices Improving Rapidly
posted on July 22, 2013 12:06
The average selling price (ASP) of DRAM chips has risen in every month this year and is now at levels last seen in October 2010, according to market research firm IC Insights.
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EUV Litho Still a Work in Progress
posted on July 22, 2013 12:05
As has been the case for the past several years, trepidation over the development of extreme ultraviolet (EUV) lithography was one of the oft-repeated themes at this year's Semicon West fab tool tradeshow in San Francisco.
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Applied Materials Launches Epi System Focused on NMOS Strain
posted on July 22, 2013 12:04
Applied Materials (AMAT) had an analyst day on Monday, and in the morning they invited a few of us to some product launches. The one that caught my eye and ear was a new epi system focused on NMOS epitaxial source/drains to create channel strain, since that has been mooted as a next step for several years now, but not shown up in a production context.
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Micron unveils 16nm Flash memory technology
posted on July 22, 2013 12:03
Micron Technology, Inc., today announced that it is sampling next-generation, 16-nanometer (nm) process technology, enabling the industry’s smallest 128-gigabit (Gb) multi-level cell (MLC) NAND Flash memory devices.
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Hybrid Memory Cube nears engineering sample milestone
posted on July 22, 2013 12:02
Engineering samples of The Hybrid Memory Cube (HMC) are expected this summer, with high volume manufacturing coming next year. It will be one of the first high volume devices employing 3D integration and through silicon vias (TSVs), employing a bottom logic layer and 4-8 stacked DRAM layers.
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